1. Field of the Invention
The present invention relates to a semiconductor device designed by arranging a plurality of cells and specifically to a cell physical structure which enables suppression of variation in transistor characteristics in a cell.
2. Description of the Related Art
In recent years, in an LSI designed under a standard cell scheme, the layout pattern and arrangement of semiconductor circuit elements have been causing greater effects on the performance of the circuit along with the advancement of semiconductor process miniaturization. Therefore, high precision is required for cell circuit design, and accordingly, the importance of CAD (Computer Aided Design) tools in circuit design is increasing. For example, a circuit simulator is one of the CAD tools which have the greatest effects on design accuracy.
The circuit simulator performs a circuit simulation based on a netlist to check whether or not cells and LSI actually operate as intended by design. Herein, the “netlist” refers to data for designed cells and LSI, including the information about connections of elements, such as transistors, capacitors, resistors, etc., the information about the characteristics of elements, such as the specifications, capacitance values and resistance values of transistors, etc. The netlist can be extracted by a netlist extractor from a mask layout of designed cells and LSI.
In the process of circuit design, the most important portion of the information included in the netlist is transistor characteristic information. The transistor characteristic information represents complicated electric characteristics of transistors (hereinafter, referred to as “transistor model”). The transistor characteristic information has to include optimized model parameters in order to precisely reproduce an actual operation of transistors.
Hereinafter, a transistor structure designed based on a conventional transistor model, a commonly-employed cell structure designed using such a transistor structure, and a semiconductor device fabricated using cells which have such a cell structure are sequentially described with reference to the drawings. FIG. 11 is a schematic view showing a transistor structure, with which a conventional transistor model is described. As shown in FIG. 11, a transistor T is formed by an impurity diffusion region Dt, which is surrounded by a device isolation region S, and a polysilicon portion P. The gate G of the transistor T is formed by the lower part of the polysilicon portion P which is sandwiched by the impurity diffusion region Dt (hatched area of polysilicon portion P). The source and drain of the transistor T are formed by the impurity diffusion region Dt. Herein, the width of the gate G is represented by Wg, the length of the gate G is represented by Lg, the width of the impurity diffusion region Dt is represented by Wd, and the length of the impurity diffusion region Dt is represented by Ld.
FIG. 12 shows a cell structure designed using the transistor structure of FIG. 11. As shown in FIG. 12, a cell C is formed by a P-type transistor Tp, an N-type transistor Tn, a device isolation region S, an interface B between a P-type transistor placement region and an N-type transistor placement region, an impurity diffusion region Dbn for supplying a substrate potential to the P-type transistor, and an impurity diffusion region Dbp for supplying the substrate potential to the N-type transistor. Cell formation generally requires other elements, such as a well, contacts, metal wires, and vias, but these elements are out of the concept of the present invention and are therefore not shown in the drawings. In FIG. 12, the impurity diffusion region Dt, the polysilicon portion P, and the gate G are not specifically indicated by the reference marks for avoidance of redundancy because they have already illustrated in FIG. 11.
The cell C shown in FIG. 12 is merely an exemplary cell. Other than this, a variety of cells having desired functions can be realized by arbitrarily arranging and wiring transistors which have various widths and lengths. FIG. 13 shows a semiconductor device including a plurality of cells. As shown in FIG. 13, cells C1, C2, C3, . . . are arranged in lines and wired in order to realize an LSI having desired functions.
In the conventional transistor model for the transistor T shown in FIG. 11, only width Wg of the gate G and length Lg of the gate G are defined as parameters. However, the current drivability of the transistor varies according to the arrangement of the impurity diffusion region Dt, and therefore, sufficient accuracy cannot be secured with the conventional transistor model. Thus, when the conventional transistor model is used, it is difficult to secure design accuracy for cells and LSI. That is, to actually achieve the LSI performance expected by design, it is necessary to model the dependency on the arrangement of the impurity diffusion region Dt and define the modeled arrangement dependency as a model parameter.
Especially in recent years, because of the use of STI (Shallow Trench Isolation) as a device isolation technique, a mechanical stress caused on a channel region of the transistor by an insulator film used in a device isolation region (hereinafter, referred to as “STI stress”) causes a variation in channel mobility depending on the largeness of the device isolation region, and accordingly, the current characteristic of the transistor greatly varies. This has been an outstanding factor which results in the dependency on the arrangement of the impurity diffusion region Dt in modeling.
Hereinafter, the relationship between the STI stress and the arrangement of the impurity diffusion region Dt is described with reference to FIG. 14. FIG. 14 shows a conventional cell structure. As shown in FIG. 14, a cell C is formed by P-type transistors Tp1, Tp2 and Tp3, N-type transistors Tn1, Tn2 and Tn3, and a device isolation region S. It should be noted that the impurity diffusion region Dt and gate G of each transistor are not specifically indicated by reference marks.
In FIG. 14, as for a portion of the device isolation region S between the impurity diffusion region of the P-type transistor Tp1 and the impurity diffusion region of the P-type transistor Tp2, the length of this portion in the gate length direction of the transistor is referred to as separation length Lsp1. Likewise, as for a portion of the device isolation region S between the impurity diffusion region of the P-type transistor Tp2 and the impurity diffusion region of the P-type transistor Tp3, the separation length is Lsp2. As for a portion of the device isolation region S between the impurity diffusion region of the P-type transistor Tp1 and the impurity diffusion region of the P-type transistor Tp3, the separation length is Lsp3. Likewise, separation length Lsn1 and separation length Lsn2 are also defined in the N-type transistor placement region as shown in FIG. 14.
As for a portion of the device isolation region S between the impurity diffusion region of the P-type transistor Tp1 and the impurity diffusion region of the N-type transistor Tn1, the length of this portion in the gate width direction of the transistor is referred to as separation width Ws1. Likewise, as for a portion of the device isolation region S between the impurity diffusion region of the P-type transistor Tp2 and the impurity diffusion region of the N-type transistor Tn2, the separation width is Ws2. As for a portion of the device isolation region S between the impurity diffusion region of the P-type transistor Tp3 and the impurity diffusion region of the N-type transistor Tn3, the separation width is Ws3.
Separation lengths Lsp1, Lsp2 and Lsp3 are different from one another. Separation width Ws1, Ws2 and Ws3 are different from one another. Even if the gates and impurity diffusion regions of the P-type transistors Tp1, Tp2 and Tp3 are all the same in shape and size, the arrangement of the impurity diffusion regions is irregular. Therefore, the effects of the STI stress on the transistors are different, so that a difference in current drivability of the transistors occurs.
If the effects of the STI stress were modeled and incorporated in the model parameters, highly-precise circuit design would be possible. When the arrangement of the impurity diffusion regions is complicated and irregular as shown in FIG. 14, detailed modeling is difficult. In such a case, design is carried out with variation in current drivability of the transistors, resulting in deteriorated design accuracy.
Thus, it is necessary to improve the accuracy of modeling by limiting the shape and arrangement patterns of the impurity diffusion regions such that the variation in current drivability of the transistors is reduced to even a small extent. For example, in a conventional technique disclosed in Japanese Laid-Open Patent Publication No. 2004-241529, the arrangement pattern of the impurity diffusion regions is limited by such a layout restriction that separation widths Ws1, Ws2 and Ws3 shown in FIG. 14 are uniform, whereby variation in transistor characteristics is suppressed.
The technique disclosed in Japanese Laid-Open Patent Publication No. 2004-241529 does not place a layout restriction as to separation lengths Lsp1, Lsp2 and Lsp3 shown in FIG. 14, and therefore does not entirely restrict the arrangement pattern of the impurity diffusion regions. Therefore, this technique cannot sufficiently suppress the variation in transistor characteristics.
This problem is described in more detail with reference to FIG. 15A and FIG. 15B which show cross-sectional views taken along line a-b and line c-d of FIG. 14. In FIG. 15A, the P-type transistor Tp1 is formed by a gate Gp1 and impurity diffusion regions Dtp1 and Dtp2, the P-type transistor Tp2 is formed by a gate Gp2 and impurity diffusion regions Dtp3 and Dtp4, and the P-type transistor Tp3 is formed by a gate Gp3 and impurity diffusion regions Dtp5 and Dtp6. The device isolation region includes a portion Sp1 which is in contact with the impurity diffusion region Dtp1, a portion Sp2 which is in contact with the impurity diffusion regions Dtp2 and Dtp3, a portion Sp3 which is in contact with the impurity diffusion regions Dtp4 and Dtp5, and a portion Sp4 which is in contact with the impurity diffusion region Dtp6. The separation length of the portion Sp2 of the device isolation region is Lsp1. The separation length of the portion Sp3 of the device isolation region is Lsp2. When the P-type transistors Tp1, Tp2 and Tp3 operate, the currents of the transistors flow through channels CH1, CH2 and CH3, respectively.
FIG. 15B is identical to FIG. 15A except that the device isolation region includes a portion Sp5 which is in contact with the impurity diffusion regions Dtp2 and Dtp5, the separation length of the portion Sp5 of the device isolation region being Lsp3.
In the channel of the transistor, strain is caused in the lattice by the STI stress. Therefore, when the stress is increased, the current drivability decreases in the channel portion. Since the STI stress depends on the separation length between the impurity diffusion regions, the transistors have different current capacities according to the variation of the separation length. In the example of FIG. 15, separation length Lsp1 and separation length Lsp2 are different. Accordingly, the effects of the STI stress on the channels CH1, CH2 and CH3 are also different, so that the transistors Tp1, Tp2 and Tp3 have different current capacities. Even within a channel of a transistor, if the separation width differs according to the arrangement of impurity diffusion regions of the transistor, the current drivability of the transistor lacks in uniformity along the channel, resulting in a varying current drivability. For example, in the example of FIG. 15, separation length Lsp1 and separation length Lsp3 are different, and accordingly, the largeness of the current of the channel CH1 passing through the cross-section taken along line a-b is different from the largeness of the current of the channel CH1 passing through the cross-section taken along line c-d. Thus, the current drivability of the transistor Tp1 lacks in uniformity along the channel CH1. As previously described, the variation in transistor characteristics caused by the STI stress cannot be reflected in the model parameters of the conventional transistor model. Therefore, the variation in transistor characteristics cannot be reproduced, resulting in deteriorated design accuracy for cells and LSI.